1. Field of the Invention
The present invention relates to a semiconductor device including a junction gate type field effect transistor(J-FET) and a heterojunction bipolar transistor(HBT) on the same semiconductor base body, and a process of fabricating such a semiconductor device.
2. Description of the Related Art
In a so-called double polysilicon type bipolar transistor, graft base regions for a base region are formed by introduction of an impurity from a first polycrystalline silicon semiconductor layer forming a base electrode on a semiconductor substrate and an emitter region is formed by introduction of an impurity from a second polycrystalline silicon semiconductor layer forming an emitter electrode on the semiconductor substrate. This improves the self-alignment of the emitter position relative to that of the base and the self-alignment of the emitter electrode position relative to that of the base electrode. Such a double polysilicon type bipolar transistor enables high speed operation by reducing device area and has been used in high speed devices.
In the case of using the above described double polysilicon type bipolar transistor as a linear device, it is necessary to form a device such as a PNP transistor or junction gate type field effect transistor as well as an NPN transistor on the same semiconductor substrate.
A process of simultaneously forming a double polysilicon type bipolar transistor and a junction gate type field effect transistor on the same semiconductor substrate is now described with reference to FIGS. 7A to 7H. First, at a step shown in FIG. 7A, an N.sup.+ -type buried diffusion layer 102 is formed by selective diffusion or the like in an upper layer of a P-type silicon semiconductor substrate 101 at a region which will be taken as a double polysilicon type bipolar transistor forming region (hereinafter, referred to as a "first region"). At the same time, an N.sup.+ -type buried diffusion layer 103 is formed by selective diffusion or the like in an upper layer of the silicon semiconductor substrate 101 at a region which will be taken as a junction gate type field effect transistor forming region (hereinafter, referred to as a "second region"). An N-type epitaxial layer 104 is then formed on the silicon semiconductor substrate 101 by an epitaxial growth process. A semiconductor base body 105 is thus formed. In addition, the N.sup.+ -type buried diffusion layers 102, 103 are also diffused on the epitaxial layer 104 side.
Next, at the next step shown in FIG. 7B, a field oxide film 107 is formed by LOCOS (local oxidation of silicon) in such a manner as to be embedded in grooves (not shown) which are formed in the epitaxial layer 104 for isolating a base region, collector contact region, and field region from each other. Then, a P-type isolation diffusion layer 108 for isolating the first region from the second region is formed at a portion extending from the epitaxial layer 104 to the silicon semiconductor substrate 101 by selective ion implantation, and a collector contact region 109 connected to the N.sup.+ -type buried diffusion layer 102 is formed in the epitaxial layer 104 by selective ion implantation.
An insulating film 110 comprised of silicon oxide or the like is formed over the surface of the semiconductor base body 105, and is etched to have openings 112, 113 positioned over active regions of the first and second regions. The process goes on to a step shown in FIG. 7C, in which a first polycrystalline silicon semiconductor layer is formed over the entire surface of the semiconductor base body 105 formed with the insulating film 110 to a thickness of, for example, about 150 nm by chemical vapor deposition (hereinafter, referred to as "CVD"), and the polycrystalline silicon semiconductor layer is doped with boron difluoride (BF.sub.2.sup.+) ions or boron (B.sup.+) ions by ion implantation to form a P-type polycrystalline silicon layer 121.
At the next step shown in FIG. 7D, the polycrystalline silicon layer 121 is patterned by lithography and reactive ion etching (hereinafter, referred to as "RIE") to be left at a portion over which will be a base region, a portion which will be a base electrode, a portion over which will be a channel region, and portions which will be source/drain electrodes. Subsequently, an insulating film 122 comprised of silicon oxide or the like is formed by CVD in a state covering the polycrystalline silicon layer 121. Then, the polycrystalline silicon layer 121 left at the portion over which will be the base region and the insulating film 122 are patterned by lithography and RIE to have a base window 123 such that the surface of the semiconductor base body 105 is exposed therethrough. The polycrystalline silicon layer 121 left at the portion over which will be the channel region and the insulating film 122 are patterned by lithography and RIE to provide a channel window 124 in such a state that the surface of the semiconductor base body 105 is exposed therethrough.
A surface layer of the semiconductor base body 105 is doped with boron difluoride (BF.sub.2.sup.+) ions or boron (B.sup.+) ions by ion implantation through the base window 123 and the channel window 124. The process goes on to a step shown in FIG. 7E, in which an insulating film 126 comprised of silicon oxide or the like is formed over the entire surface on the insulating film 122 by CVD followed by annealing to diffuse ions of the impurity contained in the polycrystalline silicon layer 121 to the upper layer of the semiconductor base body 105. This results in formation of graft base regions 127 and source/drain regions 131, 132.
The above described annealing activates ions of the impurity implanted through the base window 123, ions of the impurity implanted through the channel window 124, and ions of the impurity in the polycrystalline silicon layer 121. Thus, a base region (intrinsic base region) 128 connected to the graft base regions 127 and a base electrode 129 comprised of the polycrystalline silicon layer 121 are formed. At the same time, a channel region 133, and source/drain electrodes 134, 135 composed of the polycrystalline silicon layer 121 are formed.
At the next step shown in FIG. 7F, the insulating film 126 is etched-back to form side walls 141 on inner side walls of the base window 123 thus forming an emitter window 142, and to form side walls 143 on inner side walls of the channel window 124 thus also forming a gate window 144.
The process goes on to a step shown in FIG. 7G, in which a second polycrystalline silicon semiconductor layer 151 is formed by CVD to a thickness of, for example, about 150 nm in such a manner as to be embedded in the emitter window 142 and the gate window 144. Then, the polycrystalline silicon semiconductor layer 151 is entirely doped with phosphorus (P.sup.+) ions or arsenic (As.sup.+) ions by ion implantation, followed by annealing to form an emitter region 152 on a surface layer of the base region 128 and a gate region 153 on a surface layer of the channel region 133. The epitaxial layer 104 at a portion under the channel region 133 also forms a lower gate region.
At the next step shown in FIG. 7H, the polycrystalline silicon semiconductor layer 151 is patterned by lithography and RIE, to form an emitter electrode 161 connected to the emitter region 152 and a gate electrode 162 connected to the gate region 153. An insulating film 171 comprised of silicon oxide or the like is formed by CVD to cover the emitter electrode 161 and the gate electrode 162. Then, by lithography and RIE, the insulating film 171 is patterned to have electrode windows communicated to the emitter electrode 161 and gate electrode 162. The insulating films 171, 122 are patterned to have electrode windows communicated to the base electrode 129 and source/drain electrodes 134, 135, and the insulating films 171, 122, 110 are patterned to have an electrode window communicated to the collector contact region 109.
Finally, a metal electrode layer including a barrier metal such as aluminum (Al) or titanium (Ti)/titanium oxide-nitride (TiON)/titanium/aluminum-silicon (Al--Si) is formed and is patterned by lithography and RIE, to form a metal electrode 181 connected to the base electrode 129, a metal electrode 182 connected to the emitter electrode 161, a metal electrode 183 connected to the collector contact region 109, a metal electrode 184 connected to the source/drain electrode 134, a metal electrode 185 connected to the source/drain electrode 135, and a metal electrode 186 connected to the gate electrode 162. The double polycrystalline silicon type bipolar transistor, and the junction gate type field effect transistor can be formed on the same semiconductor base body in this manner.
In the above-described related art process, however, since the channel region of the junction gate type field effect transistor is formed simultaneously with formation of the base region of the double polysilicon type bipolar transistor, if the impurity concentration of the polycrystalline silicon layer is set at a value which is sufficient for the base region, the channel resistance (source-drain resistance) becomes larger; and since the lower gate region is formed of the N-type epitaxial layer, it has a low impurity concentration. This limits the improvement in lower gate effect, specifically the mutual conductance gm. This makes it difficult to improve an amplitude ratio of the junction gate type field effect transistor.
In the semiconductor device 201 shown in FIG. 8, a high NPN bipolar transistor 202 having improved mutual conductance gm and a junction gate type field effect transistor 203 are formed on the same semiconductor substrate 200. A base region 211 of the high NPN bipolar transistor 202 has an impurity concentration profile of a so-called LEC (Lightly Emitter Concentration) structure in which the peak of the impurity concentration distribution is located at a portion deeper than an emitter/base junction where an emitter region 212 makes a junction with the base region 211. This is accomplished by ion implantation of an impurity at a high ion implantation energy, thus making the device able to withstand high voltage.
However, in the case where the base region 211 of the high NPN bipolar transistor is formed simultaneously with formation of the channel region 231 of the junction gate type field effect transistor 203, if the impurity concentration of the base region 211 is optimized, the impurity concentration of the channel region 231 becomes lower. This results in a shortcoming in that the mutual conductance gm can be improved, however, the channel resistance is increased.